Opportunity Description
Key Responsibilities
- Constraint Development & Validation: Create, validate, and manage SDC constraints (clocks, I/O paths, generated clocks, false/multicycle paths) to accurately reflect the design's intent.
- Timing Analysis & Closure: Run full-chip and block-level STA using sign-off tools like Synopsys PrimeTime or Cadence Tempus.
- Constraint QoR Checks: Evaluate and debug timing reports to fix setup, hold, and DRC (Design Rule Checking) violations.
- Cross-Domain Analysis: Perform Clock Domain Crossing (CDC) analysis and manage constraints for asynchronous crossings.
- ECO Execution: Drive Engineering Change Orders (ECOs) by partnering with Physical Design (PD) and RTL teams.
- Scripting: Develop scripts using Tcl, Perl, or Python for automation and workflow efficiency.
Qualifications
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