Senior Verif Engineer - Memory/ASIC (SystemVerilog/UVM)

Link-Worldwide in Mexico, Jalisco, is seeking a skilled engineer to join their team in building advanced verification platforms for memory designs. The role involves creating full chip behavior models and driving innovation for future memory generations.

The ideal candidate will have a bachelor's or postgraduate degree in Electronics Engineering, along with fluency in verification languages such as System Verilog and experience in ASIC verification. The position offers an innovative work environment with a focus on collaboration.