Opportunity Description
Elevate your engineering career as a Senior Digital Verification Engineer with Ciena, focusing on innovative verification strategies for high-speed connectivity. Collaborate with a talented team to validate functional blocks and subsystems in a flexible work environment.
At Ciena, you will play a crucial role within the telecommunications industry, directly impacting the performance of our Wavelogic modem family. This position demands expertise in C/C++, System Verilog, and innovative verification techniques, as you’ll work alongside Digital Design Engineers to ensure comprehensive validation of Ciena's Forward Error Correction IP. Your contributions will drive the team's success and foster a culture of continuous improvement.
Key Responsibilities:
• Read and comprehend FEC architecture specifications
• Develop verification plans, including functional coverage
• Create testbench environments using System Verilog UVM
• Monitor regressions and debug verification failure...
At Ciena, you will play a crucial role within the telecommunications industry, directly impacting the performance of our Wavelogic modem family. This position demands expertise in C/C++, System Verilog, and innovative verification techniques, as you’ll work alongside Digital Design Engineers to ensure comprehensive validation of Ciena's Forward Error Correction IP. Your contributions will drive the team's success and foster a culture of continuous improvement.
Key Responsibilities:
• Read and comprehend FEC architecture specifications
• Develop verification plans, including functional coverage
• Create testbench environments using System Verilog UVM
• Monitor regressions and debug verification failure...
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