Opportunity Description
Enhance verification processes at Astera Labs as a Senior Design Verification Engineer, utilizing your extensive knowledge in C/C++ and UVM for groundbreaking AI connectivity solutions.
Astera Labs is in search of a highly skilled Principal Design Verification Engineer with a robust academic background in electrical engineering and substantial experience in SoC products. With a minimum of eight years in verification, you will leverage your technical expertise to communicate effectively using high-level programming languages and support RTL simulations, CoSimulation, and emulation efforts.
Key Responsibilities:
• Integrate C/C++ in System Verilog using DPI/PLI
• Automate infrastructural tasks using Perl/Python
• Develop directed and constrained random test environments
• Collaborate with RTL designers for testing
• Create user-controlled constraints in transaction-based verification
Requirements:
• Bachelor’s deg...
Astera Labs is in search of a highly skilled Principal Design Verification Engineer with a robust academic background in electrical engineering and substantial experience in SoC products. With a minimum of eight years in verification, you will leverage your technical expertise to communicate effectively using high-level programming languages and support RTL simulations, CoSimulation, and emulation efforts.
Key Responsibilities:
• Integrate C/C++ in System Verilog using DPI/PLI
• Automate infrastructural tasks using Perl/Python
• Develop directed and constrained random test environments
• Collaborate with RTL designers for testing
• Create user-controlled constraints in transaction-based verification
Requirements:
• Bachelor’s deg...
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