Opportunity Description
Lead physical design engineering at Astera Labs in Toronto, focusing on complex SoC implementations. Drive ASIC execution while mentoring a talented team within the Signal Connectivity Group.
Astera Labs seeks a Physical Design Engineering Manager with over ten years of relevant experience, including two years in team leadership. Your hands‑on expertise across the physical design flow will guide the team in implementing high-speed connectivity solutions like PCIe and Ethernet retimers. You will foster engineering talent and ensure successful implementation from RTL to GDSII.
Key Responsibilities
- Drive physical design execution from floorplan to tapeout
- Lead a team of physical design engineers in Toronto
- Ensure design convergence across multiple disciplines and vendors
- Establish best practices and quality checks for design flows
- Collaborate with global teams to maintain standards
Requirements
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