Opportunity Description
<p style="margin-bottom:11px"><b>Physical Design Engineer</b></p> <p style="margin-bottom:11px">Seeking a Physical Design Engineer in Mountain View, CA (Onsite) with strong expertise in Place & Route (PnR), timing closure, STA, and PPA optimization for advanced semiconductor designs.</p> <p style="margin-bottom:11px">Key skills include floorplanning, placement, CTS, routing, EMIR analysis, SDC constraints, signoff methodologies, and experience with EDA tools like Fusion Compiler, ICC2, PrimeTime, and Innovus.</p> <p style="margin-bottom:11px"><font face="Aptos, sans-serif"><b>Location: Mountain View, CA</b></font></p> <p style="margin-bottom:11px"><font face="Aptos, sans-serif"><b>For Immediate Consideration: </b></font></p> <p>Suryansh</p> <p>PRIMUS Global Services</p> ...
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