Opportunity Description
Unlock your potential as an Experienced Design Verification Engineer focused on display IP verification. Bring your System Verilog and UVM expertise to a rewarding contract position.
With a mid-senior level designation, this role appeals to candidates with 3 to 13 years of design verification experience. You will orchestrate the IP/SS testing and enhance quality assurance for graphics technology. Mastery of System Verilog (SV) and Universal Verification Methodology (UVM) is required for those looking to excel in this position.
Key Responsibilities:
• Oversee verification of graphics card display IP
• Execute comprehensive IP/SS and end-to-end testing
• Lead the DV flow with SV and UVM
• Collaborate on contract-driven verification projects
• Implement robust verification strategies
Requirements:
• 3-13 years experience in design verification
• Strong command of System Verilog and UVM
• Experience with IP testing and quality assurance
• Understanding o...
With a mid-senior level designation, this role appeals to candidates with 3 to 13 years of design verification experience. You will orchestrate the IP/SS testing and enhance quality assurance for graphics technology. Mastery of System Verilog (SV) and Universal Verification Methodology (UVM) is required for those looking to excel in this position.
Key Responsibilities:
• Oversee verification of graphics card display IP
• Execute comprehensive IP/SS and end-to-end testing
• Lead the DV flow with SV and UVM
• Collaborate on contract-driven verification projects
• Implement robust verification strategies
Requirements:
• 3-13 years experience in design verification
• Strong command of System Verilog and UVM
• Experience with IP testing and quality assurance
• Understanding o...
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