Hybrid Senior RTL Design Engineer - SoC & PD Lead

Cisco Silicon One Team in Armenia is hiring a senior ASIC digital design engineer. The role involves contributing to RTL design, sub-system integration, and improving design flows. You will collaborate with verification and physical design teams to deliver high-quality silicon.

Requires 6+ years in ASIC design, strong Verilog/SystemVerilog skills, and scripting in Python/Tcl/Make. Hybrid work setup includes four days at Cisco’s Yerevan office and cross-team collaboration.