Opportunity Description
The application window is expected to close on: 07/10/2026
Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received .
Hardware Engineer (hybrid) -
*onsite at San Jose CA office*
We are seeking an experienced System Level Test (SLT) Engineer to lead the design, automation, and validation of robust SLT solutions for High Volume Manufacturing (HVM) of complex, high-power, high-speed System-on-Chips (SOCs). You will play a critical role in developing and integrating automated test flows, collaborating with cross-functional teams, and ensuring seamless production test enablement and quality improvement across the product lifecycle.
Key Responsibilities:
Lead the design, automation, and validation of System Level Tests (SLT) tailored for HVM for cutting-edge, high-power, high-speed SOCs.
Develop and integrate comprehensive test flows, scri...
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