Opportunity Description
Job Description1. CPU system design and performance analysis
2. System bus architecture and integration
3. IP and system verification
4. Debug Architecture related IP design and integration
#LI-YT1
Requirement1. HDL languages (such as Verilog or VHDL) and verification languages (such as SystemVerilog, UVM).
2. Experienced in Pre-silicon signoff and Post-silicon verification and debugging.
3. Experienced in CPU system design (ARM based is better)
4. Experienced in SoC system design and silicon verification
2. System bus architecture and integration
3. IP and system verification
4. Debug Architecture related IP design and integration
#LI-YT1
Requirement1. HDL languages (such as Verilog or VHDL) and verification languages (such as SystemVerilog, UVM).
2. Experienced in Pre-silicon signoff and Post-silicon verification and debugging.
3. Experienced in CPU system design (ARM based is better)
4. Experienced in SoC system design and silicon verification
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