ASIC RTL Engineer III, Silicon, IP Subsystem

ASIC RTL Engineer III, Silicon, IP Subsystem

_corporate_fare_ Google _place_ Bengaluru, Karnataka, India

**Mid**

Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

**Minimum qualifications:**

+ Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
+ 4 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
+ 3 years of experience in ASIC design flows and methodologies, IP integration (e.g., subsystems, memories, IO's and Analog IP) and RTL design.
+ Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques.

**Preferred qualifications:**

+ Master's degree or PhD in Electrical Engineering, Computer...