Opportunity Description

Responsibilities

  • Design and implement production test solutions for mixed‑signal ASICs.
  • Develop and maintain test environment infrastructure using C and SystemVerilog.
  • Collaborate with analog and digital design teams to create and execute verification plans.
  • Develop test cases, scripts, and programs for wafer and package testing based on design specifications.
  • Debug and analyze test failures to determine root causes and improve product quality.
  • Optimize test methodologies to improve yield and reduce test time.
  • Build and automate workflows and test frameworks to improve development efficiency.

Qualifications

  • Bachelor's degree in Electrical Engineering or Computer Engineering.
  • 5+ years of experience in SystemVerilog, UVM, SVA, C/C++, and industry simulators.
  • Experience applying test techniques for DAC, ADC, and PLL components.
  • Experience in scripting for task a...
Full-time Engineering

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